Embodiments of the present disclosure relate generally to the field of semiconductor devices, and, more particularly, to power and clock gating within semiconductor devices.
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree. Pruning the clock disables portions of the circuitry so that the flip-flops or latches in them do not have to switch states. Switching states consumes power. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred. Power gating is another technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that are not in use. Clock gating and power gating can be applied to semiconductor devices.